Affected products
It's at the end of the linked-to advisory.
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3261 publicly visible posts • joined 21 Sep 2011
FYI: Congrats – you are the 150,000th comment I've manually moderated in the ~10 years I've been at The Register. The comment has the ID 4309021, so about the 4.3m'th comment we've shared.
When I started, we had to manually mod everything. Then automatic moderation was built, and still some had to be manually checked (mainly new and naughty users).
Phew.
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Yeah, it did occur to us to do some kind of 'you spin me right round' reference but we may have worn out that gag. Shocking, I know, for a Reg editor to admit that. Exhibits A through E:
You spin me right round, baby, right round like an exploding asteroid, baby, right round round round
You spin me right round, storage, right round – like a ferrous-based platter baby, round round
(Picture caption in a Lara Croft game) You spin me right round, baby, right round...
(Picture caption of a galaxy) You spin me right round ... an artist's impression of the Milky Way
(Crosshead in an Audacity review) You spin me right round....
Plus, I've had many variations of Dead or Alive's smash hit on loop in my gym playlist so I don't think I can take any more spinning right round, like a record, baby, round round, you spin me right round, like a....
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> crucial information is missing
It wasn't given, FWIW. We're not impressed by the info-lite approach to this launch.
> This Tensor chip, will I be able to buy it on Mouser or Digi-key? Is documentation going to be available?
Seriously doubt this all round. It's an SoC for this one product line.
> What kind of telemetry it is going to be sending to Google and what this chip is going to be doing with it?
The usual Android telemetry.
> How independent that third party is?
No idea.
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The advantage of RISC-V over OpenRISC is that it has more momentum, more financial backing, more corporate and enthusiast interest, and (I'm pretty sure) more hardware available now or on the horizon. It's an Arm rival that seems to have gained traction.
OpenPOWER and OpenSPARC just seem out of reach. We do keep an eye out for them. I can imagine folks feel OP and OS are a little encumbered by their parents, IBM and Oracle, respectively.
Also, Intel just reportedly tried to buy a RISC-V startup for $2bn+. I don't see that happening with OR, OP, and OS outfits.
If there's a screw-up in the RISC-V world, then let us know if we don't spot it, and we'll write about it. We're pro-competition and we like tracking things that may challenge the status quo (eg, Arm). RISC-V is still so young that it's not in widespread use and the opportunity for that community to blow it hasn't come up yet.
There may be some technical limitations to OpenRISC v RISC-V. The people who created RV complained that OR still had branch delay slots (ew), the architecture and its software stacks weren't fully 64-bit ready, and the ISA encoding space gave too much room to immediate values, which is awkward.
Sure, I hope one day we get a chance to do a technical look at RISC-V v OpenRISC v OpenPOWER v OpenSPARC, but for now, the reason why we write about RISC-V is because we like an underdog. As Arm's CEO said, RISC-V keeps Arm on its toes, which is good for everyone. OpenRISC and OpenPOWER ain't doing that.
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The neural network, Google says, outperforms human and industry automated tool placement.
So when you see in the article "beats humans" read it as "beats humans using their brains and their automated tools". I'll try to make that clearer.
Google's argument is that the neural net places macro blocks better than humans and their tools, and does it in hours, and not in a process that can take months to juggle around blocks and cells. Also, the AI can place the blocks in an unconventional manner: it seems to scatters them as needed, which some humans might not be so brave to do. The design looks like a mess but it's optimal.
FWIW it's been 15+ years since I've done any kind of chip design. In researching this piece, I read a pre-publication analysis of the paper by Andrew B. Kahng, a VLSI professor at UCSD, and for instance he mentions:
"The authors report that the agent places macro blocks sequentially, in decreasing order of size — which means that a block can be placed next even if it has no connections (physical or functional) to previously placed blocks.
"When blocks have the same size, the agent’s choice of the next block echoes the choices made by ‘cluster-growth’ methods, which were previously developed in efforts to automate floorplan design, but were abandoned several decades ago.
"It will be fascinating to see whether the authors’ use of massive computation and deep learning reveal that chip designers took a wrong turn in giving up on sequential and cluster-growth methods."
In other words, the AI works differently to humans and their automated tools, and that difference can be seen.
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Mobile phones that can't make calls. There's a demand among drug traffickers for handhelds that have had their voice call capabilities, and other functions, removed for security and privacy reasons -- preferably physically removed, if possible. See Sky ECC, which was bundled on devices that had their microphones, cameras, and GPS receivers removed.
From the AFP announcement:
"The app AN0M was installed on mobile phones that were stripped of other capability. The mobile phones, which were bought on the black market, could not make calls or send emails. It could only send messages to another device that had the organised crime app. Criminals needed to know a criminal to get a device."
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Yeah, you kinda have to take Apple's word for it for now when its people say "no one, including Apple, can see both who you are and what sites you're visiting."
Presumably the Apple security guide [PDF] will be updated with details of Private Relay for cryptographers to study and assess. That guide is usually detailed enough to determine the viability of a design.
C.
Ah, see this article about the introduction of Arm's SVE, which can support SIMD vectors that are 128 to 2048 bits in length, though this implementation for smartphones goes to 128. x86 can go up to 512 bits (see AVX)
SVE started life as vector extensions for Arm supercomputers, and is now coming to client chips in the form of SVE2 (which includes SVE).
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Yes, it's in the tail end and it's now fixed. The piece does also say that it's impossible exploit in the wild, and it's more an interesting hack than anything else. If it was going to make planes fall out of the sky, we would say so.
We're not perfect. We make mistakes just like everyone else.
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The latter (the M1 MB Air has no fans FWIW). From the blog post:
"I have 7 ARM VMs booted at once… 2 are CLI only (Photon and BSD), the others are full desktops… each is configured with 4CPU and 8GB of RAM. 6 different Linux flavors and 1 FreeBSD… MacBook Air. On battery. No fans. Yep."
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Rust performs overflow checking and panics if it happens for debug builds of projects. Non-debug release builds do not panic.
You should use the built-in checked_ methods for things like this, eg checked_add. They're available for all the primitive types, at least.
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We're not Russian media but this right here is perhaps what it may look like -- coverage of 5EYES piling into Russia.
And here. And pretty much everything written about Edward Snowden and the CIA Wikileaks materials.
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There's a group of readers and advertisers heavily into just DevOps, CI/CD, software development, and containerization, and DevClass is there to serve them. El Reg isn't everyone's cup of tea, so we created a space for them.
Having said that, we'll be more closely integrating our sister sites (like DevClass) into The Reg sometime soon, which means your Reg account will work across them, allowing you to post comments, etc. And make DC stories easier to find on the Reg home and section pages.
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