Posts by Alexander_Row 2 publicly visible posts • joined 5 Mar 2010
This technique is not novel, it has already been applied, successfully , to a real ARM9 running Linux and not to a generic SPARC reproduction on an FPGA. The required time to generate the faulty signature is much less and the scheme can be broken in minutes by a single pc. The paper has been published a _year_ ago , and it's available here : http://home.dei.polimi.it/barenghi/files/FDTC2009.pdf
Interesting , except for the fact that it's not the first time this happens : Attacks to both RSA encryption and decryption using low voltage inducted faults are presented here : http://www.computer.org/portal/web/csdl/doi/10.1109/FDTC.2009.30
And these guys did not use a cluster, but a single PC to elaborate the results in a few minutes, nor they did time the glitches in the supply voltage, they just underfed the CPU a little bit.
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