A few notes on VIPER.
VIPER was designed by RSRE Malvern (now part of Quinetq?)
Hardware wise it was implemented as a gate array (physically different wiring) and ran at 1MHz in the test version.
Software wise the PLA implemented a set of finite state machines. It was an accumulator and 2 registers architecture. It's nearest equivalent would have been the 6502
While all the high level verification seemed to work fine what scuppered them was they assumed the conversion from logic design to gate wiring was perfect and (IIRC) the development tools to do so (provided by the PLA mfg) had bugs.
Here's the thing. Although I keep hearing about how foundry processes can deliver GHz capability, and individual gate on FPGA can go very high how is it I never see an actual product (connected gates) clocking at >1GHz?
My suspicion is
a) Individual FPGA cells have acquired a lot of cruft in their design. Too much flexibility slugs raw speed.
b) FPGA cell layout on the chip hinders low latency
c) Place & Route is not nearly as good as FPGA mfg's claim it is. OK you don't have a clock driver circuit every half a dozen gates but surely you can build at least MSI level (an LS 74171 ALU was 96 gates for a 4 bit slice) that has total worst case gate delay on longest path of < 1ns?
BTW regarding "RISC" ME Conway proposed a 2 instruction processor in the 1950's for (IIRC) the Lambda calculus. In the 80's an Israeli team went to the limit with a 1 instruction machine.
Effectively every sub function in the design has its own address. Want to add 3 numbers together? MOV them to the "ACC" address. Want to zero it? Move from the "Zero adder" address.