back to article Xilinx to bust ACAP in the dome of data centres all over with uber FPGA

Xilinx is developing a monstrous FPGA that can be dynamically changed at the hardware level. The biz's "Everest" project is the development of what Xilinx termed an Adaptive Compute Acceleration Platform (ACAP), an integrated multi-core heterogeneous design that goes way beyond your bog-standard FPGA, apparently. It is being …

  1. Anonymous Coward
    Anonymous Coward

    Xilinx FPGAs finally approaching their potential that was forecast by early users in 1985. The number of gates is incredible compared (IIRC) to the original 1800 count on XC2016/XC2020***

    ***The archive of my projects is buried somewhere in the garage. The hand wire-wrapped PC ISA prototype board is just too pretty to throw away. Worked first time - with only a simple 0/1 TTL logic probe for hardware testing.

    1. TonyJ

      Ahh...wire wrapping

      Painful to do but by god it looked fantastic when it was completed, if it was done properly.

      1. Anonymous Coward
        Anonymous Coward

        Re: Ahh...wire wrapping

        "Painful to do but by god it looked fantastic [...]"

        I still have several spools of the wire - all different colours. They have that almost neon quality. Gold plated pin IC sockets too. Hate to think what they would all cost me to buy nowadays. The IBM PC ISA prototyping bare board was phenomenally expensive for what it was.

        It was a skunk work out of my own pocket - which led to a successful product for the company.

        Occasionally I dig out the primitive wire-wrap tool. It just requires a spin of the fingers to put a connection on some near enough 0.1" (2.54mm) matrix pins/wires. Easier than soldering in tight places - and easily removed later when breadboarding.

        1. TonyJ

          Re: Ahh...wire wrapping

          The wire we used to use was a kind of silvery yellow. It was almost reflective and just looked amazing.

          We all had the simplest of tools to use as well. There was something very satisfying about watching it build up but it could be a royal pig to troubleshoot (well to repair, really) :)

      2. This post has been deleted by its author

        1. TonyJ

          Re: Ahh...wire wrapping

          "...If it looked fantastic, you weren't doing it right! It should look like a birds nest. Tidy neat rows of wire are terrible for crosstalk, which is mostly h-field for these circuits. It's not a job for tidy freaks!..."

          Alas I come from a time where the stuff we wirewrapped was of such low frequencies that the only way you could get any kind of crosstalk was to accidentally short something out.

          And on top of that we had a lecturer distinctly on the OCD spectrum. He used to use a rule to measure out a very specific amount of solder for us each session and we were expected to use that and only that, for example.... happy days.

          Fair point though.

  2. Steve Todd

    Intel/Altera have a year to respond?

    I think you'll find that this is a response to Intel's hybrid Xeon/FPGA designs that have been mooted for a while now.

    https://www.nextplatform.com/2017/10/02/intel-gears-fpga-push/

  3. Anonymous Coward
    Anonymous Coward

    Sounds like...

    ... these could make a very good platform for geneticly evolved algorithms.

POST COMMENT House rules

Not a member of The Register? Create a new account here.

  • Enter your comment

  • Add an icon

Anonymous cowards cannot choose their icon

Other stories you might like