Re: GHz processor vice MHz receiver with kHz BW
With the greatest respect for the experts... do these folk (or their target audience) know what goes on in a modern multi-tasking cache-based multi-core system?
I can see that in a 1960s/70s/80s system with a few MB of memory and zero or negligible cache there may have been merit in timing-based attacks and maybe power-based attacks.
From a pragmatic real world (rather than theoretical) point of view, I'm struggling to see their relevance when the algorithm in question (and the code based on it/them) is being executed on a multi-tasking OS on a multi-core processor whose timing performance at any given point of program execution is dependent on factors outwith the control of the code/algorithm in question.
On an embedded processor running nothing but the algorithm in question, then yes there may be a plausible side channel attack using e.g. timing-related effects. Maybe.
But on a typical modern real-world system, why can't I blind the timing-based (and/or power-based) attacks simply by ensuring that the code in question is not scheduled predictably, and/or that the code in question competes unpredictably with other code and data for cache access (thereby ensuring that program execution is not predictable, and thus ensuring that side effects of program execution are not predictable)?
Suggestions, pointers to previous discussion, etc, welcome.